1. Field of the Invention
This invention relates in general to charge transfer devices using a charge coupled device and more particularly to an output structure of such device.
2. Description of the Prior Art
For the output section of a CCD charge transfer device of a solid state imager, there is employed an output section in which a so-called floating diffusion-type amplifier is formed. The circuit diagram of FIG. 1 illustrates the floating diffusion-type amplifier which is formed such that a signal charge flowing from an output terminal of a CCD transfer section 1 to a diode 2 in a floating diffusion region is obtained as a change of voltage by an output amplifier 3, in other words, a gate as illustrated in FIG. 2 of an MOS transistor M1. A precharged or so-called reset MOS transistor 4 is connected as illustrated in FIG. 1.
FIG. 2 is a plan view of the output section and FIG. 3 is a cross-sectional view taken along line A--A shown in FIG. 2. As illustrated in FIGS. 2 and 3, a semiconductor substrate 11 of, for example, n-type is provided and a semiconductor well 12 of p-type is formed thereon as shown. A plurality of n-type regions 13 are formed in the major surface of the semiconductor well 12. On the n-type regions 13, there are formed a plurality of transfer electrodes 15 mounted above a gate insulating layer 14 which may be made of SiO.sub.2 or other suitable material. This structure forms a CCD transfer section 1 as illustrated.
Two phase clock pulses .phi..sub.1 and .phi..sub.2 provide driving pulses which are supplied to the transfer electrodes 15. At the final stage of the CCD transfer section 1, there is provided an output gate portion 17 and a floating region of n+ type which is formed on the major surface of the semiconductor well 12 adjacent to the output gate portion 17. The floating diffusion region 18 is connected to a gate electrode 19 of the MOS transistor M1 which forms the output amplifier 3. A source region 20 and a drain region 21 of the MOS transistor M1 are indicated in FIG. 2. A channel stopper region 22 is provided as illustrated in FIG. 2. On the major surface of the semiconductor well 12, there is formed a precharge diffusion region 23 of n+ type which is in opposing relationship to the floating diffusion region 18. A channel forming region 24 of an n-type is formed on the major surface of the semiconductor well 12 between the regions 18 and 23. On the channel forming region 24, there is formed a precharge gate electrode 25 over the gate insulating layer 14. A precharge terminal PG is provided and a precharge drain terminal PD is also provided and an output gate terminal OG is also provided which is connected to gate portion 17.
The output gain of the floating diffusion type amplifier is determined by the floating diffusion region 18, that is the diode 2 and the ambient capacitances C.sub.B, C.sub.P, C.sub.O, C.sub.I and C.sub.in as illustrated in FIG. 1. For this case, C.sub.B designates the sum of the capacitances between the floating diffusion region 18 and the P-type semicondcutor well 12 and the capacitance between the floating diffusion region 18 and the channel stopper region 22. C.sub.P designates the capacitance between the floating diffusion region 18 and the precharge gate electrode 25 and C.sub.O represents the capacitance between the floating diffusion region 18 and the output gate electrode 17. C.sub.I represents the wiring capacitance and C.sub.in represents the input capacitance of the output amplifier 3 formed within the same semiconductor chip as the CCD transfer section.
Therefore, if the voltage gain of the amplifier 3 is A, an output V.sub.OUT which is provided when a signal charge Q enters into the floating diffusion region 18 will be: ##EQU1##
It should be noted that the decrease of the capacitances causes the output gain to increase. As illustrated in FIG. 3, the capacitance C.sub.P is the sum of a capacitance C.sub.1 between the precharge gate electrode 25 and the wiring of the gate electrode 19 of the MOS transistor M.sub.1 and the capacitance C.sub.2 between the floating diffusion region 18 and the precharge gate electrode 25.
Incidently, in the prior art structure as illustrated in FIG. 2, if the area and surrounding length of the square-shape floating diffusion region 18 are minimized and then the precharge gate electrode 25 is mounted, the contact length 1 between the floating diffusion region 18 and the precharge gate electrode 25 will be equal to the length of one side of the floating diffusion region 18. For this reason, there is a limit to decreasing the capacitance C.sub.p.